A typical example of the control circuit incorporated in a semiconductor integrated circuit is illustrated in FIG. 1 of the drawings. The semiconductor integrated circuit largely comprises a multipurpose input terminal 1 coupled in parallel to an input signal detecting circuit 2 and an output terminal 3, an inverter circuit 4 operative to produce the inverse of a detecting signal S1 appearing at a control node 5, a charge-pump circuit 6, and a gate transistor formed by an n-channel enhancement-mode MOS-type field effect transistor 7. The multipurpose input terminal 1 is supplied with an input signal S2 or a first high voltage level Vpp higher than that of the input signal S2, and the input signal detecting circuit 2 is operative to detect the input signal S2 and transfers the input signal S2 to an internal circuit 8 upon detection of the input signal S2. Moreover, when the input signal detecting circuit 2 finds the input signal S2 applied to the multipurpose input terminal 1, the detecting signal S1 goes up to a certain positive voltage level, however the detecting signal S2 remains in the ground voltage level in the absence of the input signal S2. The charge-pump circuit 6 comprises two gate transistors each formed by an n-channel enhancement-mode MOS-type field effect transistor 9 or 10, and the n-channel enhancement-mode MOS-type field effect transistors 9 and 10 have respective drain nodes coupled to a source of second high voltage level Vcc and a ground terminal, respectively. The charge-pump circuit 6 further comprises three-stages of bootstrap circuits each consisting of an n-channel enhancement-mode MOS-type field effect transistor 11, 12 or 13 and a capacitor 14, 15 or 16, and a clock signal S3 swinging its voltage level between the second high voltage level Vcc and the ground voltage level and the complementary clock signal thereof are applied to the capacitors 14 and 16 and the capacitor 15, respectively. An output node 17 of the charge-pump circuit 6 is provided between the n-channel enhancement-mode MOS-type field effect transistors 10 and 13, and the control signal S1 and the inverse thereof are applied to the respective gate electrodes of the n-channel enhancement-mode MOStype field effect transistors 9 and 10, respectively. The input signal detecting circuit 2, the inverter circuit 4, the charge-pump circuit 6 and the n-channel enhancement-mode MOS-type field effect transistor 7 as a whole constitute a control circuit for the multipurpose input terminal 1.
The prior-art control circuit thus arranged allows the input signal S2 and the first high voltage level Vpp to be selectively transferred from the multipurpose input terminal 1 to the internal circuit 8 and the output terminal 3, respectively. Namely, when the input signal S2 appears at the multipurpose input terminal 1, the input signal detecting circuit 2 transfers the input signal S2 to the internal circuit 8 but the n-channel enhancement-mode MOS-type field effect transistor 7 is turned off with the ground voltage level supplied from the charge-pump circuit 6 because the detecting signal S1 goes up to the certain positive voltage level, thereby allowing the n-channel enhancement-mode MOS-type field effect transistor 10 to turn on. On the other hand, when the first high voltage level Vpp is applied to the multipurpose input terminal 1, the detecting signal S1 remains in the ground voltage level but the inverter circuit 4 produces the inverse signal of the certain positive voltage level, so that the n-channel enhancement-mode MOS-type field effect transistor 9 turns on, and, on the other hand, the n-channel enhancement-mode MOS-type field effect transistor 10 turns off with the detecting signal S1 of the ground voltage level directly supplied form the node 5. When the n-channel enhancement-mode MOS-type field effect transistor 9 turns on, the three-stages of the bootstrap circuits is activated and a voltage level V17 at the output node 17 is increased to an extremely high voltage level Vhh which is higher than the first high voltage level Vpp by at least the threshold voltage of the n-channel enhancement-mode MOS-type field effect transistor 7. Then, the first high voltage level Vpp appears at the output terminal 3 without reduction in voltage level.
In this instance, the charge-pump circuit 6 is provided with the three-stages of the bootstrap circuits, however more than three-stages of the bootstrap circuits are preferable in a practical application. In detail, assuming now that first and second high voltage levels Vpp and Vcc are 12.5 volts and 5.0 volts, respectively, and that each of the n-channel enhancementmode MOS-type field effect transistors has the threshold voltage Vth of 1.0 volt, the extremely high voltage level Vhh boosted up by the three-stages of the bootstrap circuits is calculated as follows EQU Vhh=4.times.(Vcc-Vth)=16.0 volts
Then, the first high voltage level Vpp is transferred to the output terminal 3 without reduction in voltage level.
However, if the charge-pump circuit is provided with two-stages of the bootstrap circuits, the extremely high voltage level Vhh is calculated as follows on the same assumptions EQU Vhh=3.times.(Vcc-Vth)=12.0 volts
This results in that the first high voltage level Vpp is transferred from the multipurpose input terminal 1 to the output terminal 3 with reduction in voltage level. Thus, a three-stage bootstrap circuit theoretically in recessary to transfer the first high voltage level Vpp without reduction in voltage level.
However, when the control circuit is fabricated on a semiconductor substrate ( not shown ) together with the internal circuit 8, the extremely high voltage level Vhh should be calculated in consideration of the back gate biasing effect which reduces the effective gate biasing voltage applied to each of the n-channel enhancement-mode MOS-type field effect transistors. Moreover, a design margin should be taken into account, so that four or five-stages of the bootstrap circuits are necessary to produce the extremely high voltage level Vhh sufficient to cause the channel layer to take place in the n-channel enhancement-mode MOS-type field effect transistor 7 for transferring the first high voltage level Vpp without reduction in voltage level. For this reason, a problem is encountered in the prior-art control circuit in that a large real estate is consumed with the charge-pump circuit 6.